/*
* Fallback device tree for NVIDIA Tegra X1 (ODNX2-A2) / Nintendo Switch HAC-001.
*
* NOTE: hekate's L4T loader boots from a device-tree image (nx-plat.dtimg), not
* this file, so this tree is only used for direct U-Boot / manual `booti`
* experiments. It is intentionally minimal and does NOT describe the Switch
* DSI panel, so it cannot bring up the display on its own.
*/
/dts-v1/;
/ {
compatible = "nvidia,tegra210";
model = "Nintendo Switch (Tegra X1 ODNX02-A2)";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
chosen {
bootargs = "console=ttyS0,115200n8 console=tty0 root=/dev/mmcblk0p2 rw rootwait loglevel=7 earlycon=uart8250,mmio32,0x70006000";
stdout-path = "/serial@70006000";
};
memory@80000000 {
device_type = "memory";
/* 8 GiB at 0x80000000: 0x2_00000000 bytes. */
reg = <0x0 0x80000000 0x2 0x00000000>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
gic: interrupt-controller@50041000 {
compatible = "arm,gic-400";
reg = <0x0 0x50041000 0x0 0x1000>,
<0x0 0x50042000 0x0 0x2000>,
<0x0 0x50044000 0x0 0x2000>,
<0x0 0x50046000 0x0 0x2000>;
interrupts = <1 9 0xf04>;
interrupt-controller;
#interrupt-cells = <3>;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
enable-method = "psci";
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
enable-method = "psci";
};
cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x102>;
enable-method = "psci";
};
cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x103>;
enable-method = "psci";
};
};
serial@70006000 {
compatible = "nvidia,tegra210-uart";
reg = <0x0 0x70006000 0x0 0x40>;
reg-shift = <2>;
/* GIC_SPI=0, irq=36, LEVEL_HIGH=4 */
interrupts = <0 36 4>;
status = "okay";
};
gpio: gpio@6000d000 {
compatible = "nvidia,tegra210-gpio";
reg = <0x0 0x6000d000 0x0 0x1000
0x0 0x6000d100 0x0 0x1000
0x0 0x6000d200 0x0 0x1000
0x0 0x6000d300 0x0 0x1000
0x0 0x6000d400 0x0 0x1000>;
/* GIC_SPI=0, irq=47, LEVEL_HIGH=4 */
interrupts = <0 47 4>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
};
/* eMMC */
sdhci@700b0000 {
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
/* GIC_SPI=0, irq=15, LEVEL_HIGH=4 */
interrupts = <0 15 4>;
status = "okay";
};
/* SD card */
sdhci@700b0600 {
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0600 0x0 0x200>;
/* GIC_SPI=0, irq=17, LEVEL_HIGH=4 */
interrupts = <0 17 4>;
status = "okay";
};
/* GPU (Maxwell) */
gpu@57000000 {
compatible = "nvidia,tegra210-gm20b";
reg = <0x0 0x57000000 0x0 0x1000000>;
/* GIC_SPI=0, irq=157, EDGE_RISING=1 */
interrupts = <0 157 1>;
status = "okay";
};
/* Display SOR */
sor@54580000 {
compatible = "nvidia,tegra210-sor";
reg = <0x0 0x54580000 0x0 0x40000>;
/* GIC_SPI=0, irq=97, LEVEL_HIGH=4 */
interrupts = <0 97 4>;
status = "okay";
};
/* RTC */
rtc@7000e000 {
compatible = "nvidia,tegra210-rtc";
reg = <0x0 0x7000e000 0x0 0x100>;
/* GIC_SPI=0, irq=2, EDGE_RISING=1 */
interrupts = <0 2 1>;
status = "okay";
};
/* Timer */
timer@7000e400 {
compatible = "arm,cortex-a15-timer";
reg = <0x0 0x7000e400 0x0 0x20>;
/* GIC_PPI=1, cpu_mask=0x208 (cpumask=8 << 8 | LEVEL_LOW=8) */
interrupts = <1 13 0x208>,
<1 14 0x208>,
<1 11 0x208>,
<1 10 0x208>;
clock-frequency = <19200000>;
always-on;
};
/* Clock controller */
clk: clock@60006000 {
compatible = "nvidia,tegra210-car";
reg = <0x0 0x60006000 0x0 0x1000>;
#clock-cells = <1>;
};
/* Memory controller */
mc: mc@70019000 {
compatible = "nvidia,tegra210-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
/* GIC_SPI=0, irq=77, LEVEL_HIGH=4 */
interrupts = <0 77 4>;
};
/* PWM */
pwm@7000a000 {
compatible = "nvidia,tegra210-pwm";
reg = <0x0 0x7000a000 0x0 0x1000>;
/* GIC_SPI=0, irq=45, LEVEL_HIGH=4 */
interrupts = <0 45 4>;
#pwm-cells = <2>;
status = "okay";
};
};