From 2903f2d0e28ebfd671223fe8ae2193e9a3262fa8 Mon Sep 17 00:00:00 2001
From: Pierre Tardy <[email protected]>
Date: Sun, 6 May 2018 14:16:36 +0200
Subject: [PATCH 062/124] platform integration for switch panel
---
drivers/clk/tegra/clk-tegra210.c | 5 +++++
drivers/gpu/drm/tegra/dsi.c | 37 +++++++++++++++++++++++++++++---
2 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 7545af763d7a..89578af13e5c 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -3377,6 +3377,11 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
{ TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
{ TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
+ { TEGRA210_CLK_CLK72MHZ, TEGRA210_CLK_PLL_P_OUT3, 68000000, 0 },
+ { TEGRA210_CLK_DSIALP, TEGRA210_CLK_PLL_P, 68000000, 0 },
+ { TEGRA210_CLK_DSIBLP, TEGRA210_CLK_PLL_P, 68000000, 0 },
+ { TEGRA210_CLK_DISP1, TEGRA210_CLK_PLL_D_OUT0, 0, 0 },
+ { TEGRA210_CLK_DISP2, TEGRA210_CLK_PLL_D_OUT0, 0, 0 },
/* This MUST be the last entry. */
{ TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
};
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index ee6ca8fa1c65..f516acb4b9ca 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -321,7 +321,7 @@ static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
/*
* non-burst mode with sync events
*/
-static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
+static const u32 pkt_seq_video_non_burst_sync_events_eotp[NUM_PKT_SEQ] = {
[ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
PKT_LP,
@@ -348,6 +348,32 @@ static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
[11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
};
+/*
+ * non-burst mode with sync events
+ */
+static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
+ [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
+ PKT_LP,
+ [ 1] = 0,
+ [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
+ PKT_LP,
+ [ 3] = 0,
+ [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
+ PKT_LP,
+ [ 5] = 0,
+ [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
+ PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
+ PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
+ [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
+ [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
+ PKT_LP,
+ [ 9] = 0,
+ [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
+ PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
+ PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
+ [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
+};
+
static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
[ 0] = 0,
[ 1] = 0,
@@ -505,8 +531,13 @@ static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
pkt_seq = pkt_seq_video_non_burst_sync_pulses;
} else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
- DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
- pkt_seq = pkt_seq_video_non_burst_sync_events;
+ if (!(dsi->flags & MIPI_DSI_MODE_EOT_PACKET)) {
+ DRM_DEBUG_KMS("Non-burst video mode with sync events and EOTp\n");
+ pkt_seq = pkt_seq_video_non_burst_sync_events_eotp;
+ } else {
+ DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
+ pkt_seq = pkt_seq_video_non_burst_sync_events;
+ }
} else {
DRM_DEBUG_KMS("Command mode\n");
pkt_seq = pkt_seq_command_mode;
--
2.20.1